Cadence Announces 8533Mbps LPDDR5X IP Solution for Next-Gen AI, Automotive and Mobile Applications
December 23, 2022 | Cadence Design Systems, Inc.Estimated reading time: 1 minute
Cadence Design Systems, Inc. announced the first LPDDR5X memory interface IP design optimized to operate at 8533Mbps—up to 33% faster than the previous generation of LPDDR IP. Available now for customer engagements, the Cadence® LPDDR5X IP boasts a new high-performance, scalable and adaptable architecture based on Cadence’s proven and highly successful LPDDR5 and GDDR6 product lines. The new Cadence LPDDR5X memory IP solution consists of a silicon-proven PHY and high-performance controller designed to connect to LPDDR5X DRAM devices that follow the JEDEC JESD209-5B standard. The controller/PHY interface is based on the latest DFI 5.1 specification, and a variety of on-chip buses are supported.
LPDDR5X memory opens up a wide variety of high-bandwidth applications beyond the mobile market traditionally served by LPDDR memory, including advanced driver assistance systems (ADAS), autonomous driving, lower-end edge AI and networking. Cadence LPDDR5X IP is designed to enable the industry’s next-generation SoC designs for these and other applications with flexible floorplan design options, while the new architecture allows fine-tuning of power and performance based on individual application requirements.
Cadence design IP supports the fastest data rate defined by the JEDEC standard (JESD209-5B). Cadence’s LPDDR5X Controller and PHY have been verified with Cadence’s Verification IP (VIP) for LPDDR5X to provide rapid IP and SoC verification closure. Cadence VIP for LPDDR5X includes a complete solution from IP to system-level verification with DFI VIP, LPDDR5X memory model and System Performance Analyzer.
“LPDDR5X’s peak speeds will raise the bar for device experiences and performance at the edge, from automotive to consumer IoT to networking devices,” said Michael Basca, vice president of products and systems in Micron’s Embedded Business Unit. “Our collaboration with Cadence will accelerate ecosystem adoption of LPDDR5X by enabling the next wave of chipsets to work seamlessly with this low-power, high-performance memory.”
“Cadence LPDDR5X IP operating at 8533Mbps in silicon showcases Cadence’s next-generation architecture for complete memory system IP solutions,” noted Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “This new leading-edge memory IP solution solidifies our memory interface IP leadership by enabling the industry’s future AI, automotive and mobile SoC designs today.”
The LPDDR5X IP supports Cadence’s Intelligent System Design™ strategy, which enables SoC design excellence with high-performance, design-optimized, best-in-class technology.
Suggested Items
Real Time with… IPC APEX EXPO 2024: Ventec Discusses New Pro-bond Family of Advanced Products
05/01/2024 | Real Time with...IPC APEX EXPOChris Hanson, Ventec's Global Head of IMS Technology, outlines the launch of four pro-bond formulas that deliver an outstanding combination of low dissipation factor (Df) with a dielectric constant (Dk) range to maximize the design window for critical PCB parameters. As Chris points out, Pro-bond is designed for low-loss, high-speed applications, while thermal-bond dissipates heat from a component through the board to a heat sink.
IPC's Vision for Empowering PCB Design Engineers
04/30/2024 | Robert Erickson, IPCAs architects of innovation, printed circuit board designers are tasked with translating increasingly complex concepts into tangible designs that power our modern world. IPC provides the necessary community, standards framework, and education to prepare these pioneers as they explore the boundaries of what’s possible, equipping engineers with the knowledge, skills, and resources required to thrive in an increasingly dynamic field.
On the Line With… Talks With Cadence Expert on SI/PI for PCB Designers
05/02/2024 | I-Connect007In “PCB 3.0: A New Design Methodology—SI/PI for PCB Designers,” subject matter expert Brad Griffin, Cadence Design Systems, discusses how an intelligent system design methodology can move some signal and power integrity decision-making into the physical design space, offering real-time feedback.
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.
Cadence, TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
04/25/2024 | Cadence Design SystemsCadence Design Systems, Inc. and TSMC have extended their longstanding collaboration by announcing a broad range of innovative technology advancements to accelerate design, including developments ranging from 3D-IC and advanced process nodes to design IP and photonics.