AI-designed Chips Reach Scale with First 100 Commercial Tape-outs Using Synopsys Technology
February 7, 2023 | PRNewswireEstimated reading time: 2 minutes
Synopsys, Inc. reaches scale for AI-driven chip designs as major semiconductor customers register the first 100 commercial tape-outs with the company's award-winning Synopsys DSO.ai autonomous design system. Recent customers, including STMicroelectronics and SK hynix, have all seen significant uplifts in productivity and PPA, and are now charting a new design course using reinforcement learning-enabled design tools on cloud and on-premise.
By using Synopsys DSO.ai (Design Space Optimization AI) the companies are setting a blistering pace for the development of advanced-node chips through the key design phases. Results from customers since the launch of Synopsys DSO.ai speak for themselves: more than 3x productivity increases, up to 25% lower total power and significant reduction in die size, with reduced use of overall resources.
STMicroelectronics (ST), a global semiconductor leader serving customers across the spectrum of electronics applications, is using cloud-based versions of DSO.ai to generate extra momentum on the most intensive design phases. STMicroelectronics taped-out using Synopsys DSO.ai coupled with Synopsys Fusion Compiler™ and Synopsys IC Compiler™ II physical implementation tools.
"Using the Synopsys DSO.ai design system on Microsoft Azure, we increased PPA exploration productivity by more than 3x, allowing us fast implementation of a new Arm core, while exceeding power, performance and area goals," said Philippe d'Audigier, system-on-chip hardware design director at STMicroelectronics. "We look forward to accelerating our collaboration with Synopsys and Microsoft as we explore more opportunities for new industry-leading chip designs for key projects, including ST's industrial MPUs."
Pushing Silicon Performance and Productivity
Traditional design space exploration has been a highly labor-intensive effort, typically requiring months of experimentation. Using AI technology, Synopsys DSO.ai searches design spaces autonomously to discover optimal PPA solutions, massively scaling the exploration of choices in chip design workflows and automating many menial tasks.
"Delivering high-performance, robust memory products at industry-leading volumes demands intensive optimization, which has traditionally been highly human intensive," said Junhyun Chun, head of SoC (System on Chip) at SK hynix. "Synopsys DSO.ai brings a huge amount of design team efficiency, giving our engineers more time to create differentiated features for our next generation of products. It's also driving fantastic results as demonstrated in a recent project where DSO.ai delivered a 15% cell area reduction and a 5% die shrink."
"AI's ability to explore broader design spaces is accelerating our customers' relentless drive towards better PPA and higher productivity with fewer engineering resources," said Shankar Krishnamoorthy, GM for the EDA Group at Synopsys. "We've monitored the first 100 commercial tape-outs by customers using Synopsys DSO.ai and the results are compelling. Whether they're designing in the cloud, on-premise or a hybrid of the two, it's clear that in every case, designers are seeing significant gains from optimized designs delivering better results and faster time-to-market. The cloud-side is particularly exciting as deploying Synopsys AI technology at scale in data centers ushers an exciting new era for designers everywhere."
"Microsoft is committed to democratizing advanced chip design, so it was a natural move for us to host the Synopsys DSO.ai design system on Azure," said Jean Boufarhat, corporate vice president, engineering, Azure Hardware and Infrastructure at Microsoft. "With AI-powered chip design on Azure, companies can leverage cloud-scaling to boost productivity and optimize very large solution spaces like high-performance computing."
Suggested Items
Real Time with… IPC APEX EXPO 2024: My Role as a Technology Solutions Director
05/02/2024 | Real Time with...IPC APEX EXPOPeter Tranitz, senior director of technology solutions at IPC, shares insights into his role as the design initiative lead. He details his advocacy work, industry support, and the responsibilities of the design initiative committee. The conversation also covers the revamping of standards, the IPC Design Competition, and the implementation of design rules in software tools.
Real Time with… IPC APEX EXPO 2024: Ventec Discusses New Pro-bond Family of Advanced Products
05/01/2024 | Real Time with...IPC APEX EXPOChris Hanson, Ventec's Global Head of IMS Technology, outlines the launch of four pro-bond formulas that deliver an outstanding combination of low dissipation factor (Df) with a dielectric constant (Dk) range to maximize the design window for critical PCB parameters. As Chris points out, Pro-bond is designed for low-loss, high-speed applications, while thermal-bond dissipates heat from a component through the board to a heat sink.
IPC's Vision for Empowering PCB Design Engineers
04/30/2024 | Robert Erickson, IPCAs architects of innovation, printed circuit board designers are tasked with translating increasingly complex concepts into tangible designs that power our modern world. IPC provides the necessary community, standards framework, and education to prepare these pioneers as they explore the boundaries of what’s possible, equipping engineers with the knowledge, skills, and resources required to thrive in an increasingly dynamic field.
On the Line With… Talks With Cadence Expert on SI/PI for PCB Designers
05/02/2024 | I-Connect007In “PCB 3.0: A New Design Methodology—SI/PI for PCB Designers,” subject matter expert Brad Griffin, Cadence Design Systems, discusses how an intelligent system design methodology can move some signal and power integrity decision-making into the physical design space, offering real-time feedback.
iNEMI Packaging Tech Topic Series: Role of EDA in Advanced Semiconductor Packaging
04/26/2024 | iNEMIAdvanced semiconductor packaging with heterogenous integration has made on-package integration of multiple chips a crucial part of finding alternatives to transistor scaling. Historically, EDA tools for front-end and back-end design have evolved separately; however, design complexity and the increased number of die-to-die or die-to-substrate interconnections has led to the need for EDA tools that can support integration of overall design planning, implementation, and system analysis in a single cockpit.