Tachyum Achieves 90% of Silicon Laid for its Prodigy Universal Processor
May 12, 2020 | Business WireEstimated reading time: 2 minutes
Semiconductor startup Tachyum Inc. announced today that it has achieved, on schedule, a major milestone in the detailed physical design of its Prodigy Universal Processor. Tachyum now has a complete chip layout, with a verified detailed physical design of more than 90% of the design silicon area.
Tachyum’s Prodigy is the world’s first Universal Processor, combining general-purpose processors, high-performance computing (HPC), artificial intelligence (AI), deep machine learning (ML), explainable AI, bio AI and other AI disciplines within a single chip. This latest milestone achieved integration of key, high-quality Tachyum IP within a multiprocessor environment, and with DDR4/DDR5 DRAM controllers, PCIE 5.0, 112Gb SERDES, USB, GPIO, PLLs and various I/Os. Results of the layout indicate that Prodigy’s die size is within product design goals with top-level clocking results that are better than expected.
“Next-generation leading-edge AI CPU SoCs need to integrate high-performance IP solutions that meet a range of specialized processing, memory performance and real-time data connectivity design requirements inclusive of high-speed 112G PAM4 SerDes,” said Rishi Chugh, vice president of product marketing, IP Group at Cadence. “Cadence’s best-in-class IP portfolio solutions are silicon proven in advanced process nodes and deliver optimal design productivity, enabling Tachyum to accelerate their development cycle and differentiate in the fast-moving AI market.”
“With die size and clock speed both being on target, we are confident in our ability to deliver the world’s first universal processor. It will radically improve compute performance and efficiency for data center, AI and HPC workloads,” said Tachyum CEO Dr. Radoslav Danilak.
Prodigy, the company’s 64-core flagship product, is scheduled for high-rate production in 2021. It outperforms the fastest Xeon processors at 10x lower power (core vs. core) on data center workloads, as well as outperforming NVIDIA’s fastest GPU on neural net AI training and inference. Due to its high computational density and I/O bandwidth, networks of Prodigy processors comprising of just 125 HPC racks, can deliver an ExaFLOPS (a billion, billion floating point operations per second) of capacity. Prodigy’s 3X lower cost per MIPS, compared to other CPU competition, coupled with its 10X processor power savings translates to a 4X reduction in Data Center TCO (Annual Total Cost of Ownership: CAPEX + OPEX). Even at 50% Prodigy attach rates, this translates to billions of dollars per year in real savings for hyperscalers such as Google, Facebook, and Amazon.
Since Prodigy can seamlessly and dynamically switch from data center workloads to AI or HPC workloads, unused servers can be powered up, on demand, as ad hoc AI or HPC networks—CAPEX free, since the servers themselves are already purchased. Every Prodigy-provisioned data center, by definition, becomes a low-cost AI center of excellence, and a low-cost HPC system.
Suggested Items
Cadence, TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
04/25/2024 | Cadence Design SystemsCadence Design Systems, Inc. and TSMC have extended their longstanding collaboration by announcing a broad range of innovative technology advancements to accelerate design, including developments ranging from 3D-IC and advanced process nodes to design IP and photonics.
Ansys, TSMC Enable a Multiphysics Platform for Optics and Photonics, Addressing Needs of AI, HPC Silicon Systems
04/25/2024 | PRNewswireAnsys announced a collaboration with TSMC on multiphysics software for TSMC's Compact Universal Photonic Engines (COUPE). COUPE is a cutting-edge Silicon Photonics (SiPh) integration system and Co-Packaged Optics platform that mitigates coupling loss while significantly accelerating chip-to-chip and machine-to-machine communication.
Siemens’ Breakthrough Veloce CS Transforms Emulation and Prototyping with Three Novel Products
04/24/2024 | Siemens Digital Industries SoftwareSiemens Digital Industries Software launched the Veloce™ CS hardware-assisted verification and validation system. In a first for the EDA (Electronic Design Automation) industry, Veloce CS incorporates hardware emulation, enterprise prototyping and software prototyping and is built on two highly advanced integrated circuits (ICs) – Siemens’ new, purpose-built Crystal accelerator chip for emulation and the AMD Versal™ Premium VP1902 FPGA adaptive SoC (System-on-a-chip) for enterprise and software prototyping.
Listen Up! The Intricacies of PCB Drilling Detailed in New Podcast Episode
04/25/2024 | I-Connect007In episode 5 of the podcast series, On the Line With: Designing for Reality, Nolan Johnson and Matt Stevenson continue down the manufacturing process, this time focusing on the post-lamination drilling process for PCBs. Matt and Nolan delve into the intricacies of the PCB drilling process, highlighting the importance of hole quality, drill parameters, and design optimization to ensure smooth manufacturing. The conversation covers topics such as drill bit sizes, aspect ratios, vias, challenges in drilling, and ways to enhance efficiency in the drilling department.
Elevating PCB Design Engineering With IPC Programs
04/24/2024 | Cory Blaylock, IPCIn a monumental stride for the electronics manufacturing industry, IPC has successfully championed the recognition of the PCB Design Engineer as an official occupation by the U.S. Department of Labor (DOL). This pivotal achievement not only underscores the critical role of PCB design engineers within the technology landscape, but also marks the beginning of a transformative journey toward nurturing a robust, skilled workforce ready to propel our industry into the future.