Figure It Out: Field-Programmable Battery Array (Unsolved)

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I went into the field of engineering to solve problems and come up with practical solutions. But every now and then, a solution comes up that is today unbuildable. I would like to introduce you to a problem that has been bouncing around in my head: the field-programmable battery array.

One of the notable design challenges with this is the limitations of today’s transistors. I fully acknowledge that this design is impractical today, but with better transistors (or a better designer), that could change. As history shows us, anyone who has bet against the advancement of transistors has been disappointed, so I hold hope that one day, this idea will be practical. This is more of a thought experiment, but perhaps one of you can get further with it than I have. Let’s dive in.

Since the days of Edison and Tesla, AC and DC power have been at odds. That is still true today but with some modern twists. Battery systems require a DC current for charging, but high-power transmission over practical distances is only possible with AC. At some point, that AC must be converted to DC and is a whole specialty. Converters are getting better, especially with silicon carbide and gallium nitride transistors; however, there is still a bit of bulk and weight in high-power converters. This is where the field-programmable battery array comes in.

What if the cells in a battery pack could be electrically rearranged on the fly to fit the AC input? The core idea is that instead of having a fixed number of series and parallel cells, the battery management system can rearrange the pack configuration in sync with a high voltage AC input to manage charge voltage, current, and cell balance.

A pack capable of this would need to efficiently rearrange tens or hundreds of cells to be viable (and I’m glossing over some of the nuances of charge regulation, but I don’t want to get too far into those weeds here). Having software control over the pack configuration also enables you to have control over the output(s) of the pack, and those outputs can be time-varying. Imagine configuring three outputs with varying voltage to directly drive a three-phase motor directly from the battery pack!

Before creating an entire array, let’s look at the simplest possible solution that allows a two-cell pack to switch between series and parallel configurations. Figure 1 shows two cells and three switches.


Figure 1: Two-cell battery array.

This is a simple scenario, and being able to switch between series and parallel is easy to visualize with the truth table. We found out that things get a bit trickier when you move up to three cells. Multiple solutions begin to emerge, and even the option for simultaneous voltage outputs.


Figure 2: Three-cell battery array.

This configuration allows for three different voltage levels and for any two cells to be in series. Additional terminals at specific nodes would allow for simultaneous outputs. If A and B are in series, a lower voltage can be supplied by C at a separate terminal. We can also see that since any cell can be paralleled with an adjacent cell, cell balancing becomes possible!

Of notable disappointment, this switch configuration does not permit paralleling A and C. We are starting to see the cracks in this arrangement but also the possibilities. Things get interesting at the six-cell level when we start to explore multiple terminals.


Figure 3: Six-cell battery array.

I will take a move from college textbooks and leave the truth table exercise for this configuration to the reader. Twenty switches are manageable but start to make the figures intimidating walls of 1s and 0s. I believe that a more efficient configuration is possible, though, and pose this to the design community.

It’s advantageous for the negative terminal to be on the opposite physical side of the pack than the positive terminal, at least in terms of power bussing. This permits the IR drop across the bus connections to remain balanced. For instance, in Figure 4, the sum of the wire length for both cells are illustrated. Neglecting this will force some cells to become imbalanced as the pack is depleted.


Figure 4: Balancing IR losses in interconnects.

The effectiveness of any switch configuration can be measured by how effectively it addresses these design targets, geared to reduce losses:

  1. Minimize the number of required switches.
  2. Minimize the power losses in any one switch.
  3. Minimize the total interconnect lengths.
  4. Maximize the number of cell configurations.
  5. Maximize the maximum power available from the pack.

To you, the designer, I challenge you to conceive of a better pack and switch configuration. The one here only expands in one dimension, but there are three dimensions to work with and switch configurations that are not addressed at all here.

Bonus challenge: Can you think of a way to realize this topology using only NMOS devices?

Dugan Karnazes is the founder and CEO of Velocity Research.


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