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Whether you have two layers or 50 layers, it all comes down to how the layers communicate. Otherwise, you just have a bunch of two-dimensional layers, and that isn’t practical. The practical magic, of course, is plated drilled holes. Through the early years, it was all holes and large analog components with 16–18 layers being state of the art. Standard holes for components were usually 0.060” and spaced 0.100”. That was then. Today, the larger holes are left for connectors and hardware, with almost all componentry evolving to SMT.
Now, our plated holes are used for interconnects or vias. Although some may still accept components, they mainly provide the Z-axis connection between layers. Unlike vias of earlier times, these holes have become extremely small. In fact, some vias don’t even go through the board any longer. Some may go from the surface to a layer somewhere in the stack, where others are not visible from either side. Even though the holes have become smaller, the board thicknesses have not. From a plating engineering standpoint, this has become challenging as the aspect ratios have become very high. Each layer can be perfectly developed and etched, all to be scuttled by a bad interconnect or via. The entire board ends up being scrapped. This can be costly (Figure 1)
Although some would argue that electrical test (ET), what with all the mystical voodoo that goes on, is not a value-added process; in some aspects, they are correct. However, think of it more as an insurance policy. Having a finished board fail at a customer site or CM is the worst thing that can happen. Not only must you deal with the returned product, but you also take one on the nose for delivered quality. It can be difficult to recover from that in this competitive market. How is ET guaranteeing you the peace of mind that what you are shipping isn’t getting pickled by the barrel?
Well, there are couple things we are doing in addition to the standard continuity and isolation test. Industry standards specify the minimum requirements to which the product must conform. Remember, these are minimums. Higher-reliability products may require more stringent testing. For example, Class 2 Level B products allow the optimization of mid-points during ET, where Class 3 Level C does not. There are some options in ET that can be added to reduce the risk of rejection once the product leaves the manufacturer (Figure 2).
Forced Barrel Test
Although Class 3 Level C products do not allow the optimization of mid-points, it is not specific on how the mid-point is tested. Most ET rasterization routines will follow the circuit from end-to-end and place test points at the endpoints. If optimization is not allowed, the system will place test points at all intermediate test points along the net. However, this is based on the accessibility of the mid-points. The drawback is that if a mid-point is a via, it may test one side or the other depending on the accessibility (solder mask).
When one side of the via is covered, it’s straight forward; the open side receives a test point. The lottery here, though, is if both sides are clear most systems will place the test point on one side or the other randomly. The vulnerability here is that if the test point is placed on one side and the assembly house uses the same via as an in-circuit test (ICT) point but probed from the other side, the standard ET at the manufacture can pass, but the ECT test at the assembler can fail. How can this be?
The answer is that the test on the ICT side of the via could be voided. The barrel on the ET side may still be intact and pass the circuit through the interconnect(s) but is voided above the circuit path. This is undetectable in standard ET, even with mid-point optimization removed. The mid-point is tested, and the circuit is valid. However, the ICT test fails.
In reality, the board is fully functional but cannot be verified at the assembler and is therefore rejected. What we can do is force the barrel test. Regardless of the standard test, the barrel test can be added. Once the barrel test is activated, the user can select the drill size or the range of sizes to be checked. Now, there are some requirements for the forced test to be of value.
As I stated previously, both sides of the barrel must be accessible. This is a straightforward continuity test based on the parameters selected for the full test. This option just forces the side-to-side barrel test to capture the possible electric
al null area of a via void escaping. This test is not to be confused with 4-wire Kelvin. This test option will capture full void scenarios and not necessarily thin copper or taper plate conditions.
Kelvin 4-wire testing is all the buzz now in printed circuits. One of the most difficult defects to capture is the latent barrel void. It is common for this defect to hide and miss detection during normal ET. Most ET specifications require continuity of circuits to pass at a minimum of 5 ohms continuity at the stricter end of the spectrum (Figure 3).
With plated drilled holes, the difference between a conforming barrel and a non-conforming barrel will be in the milli-ohm range. The standard continuity parameters will not be able to detect these issues, as the difference in resistance will not be detected as it will be masked by parasitic resistance and limitations of the standard metering systems being used. The specific detects are taper plate and micro-fractures.
This is where 4-wire Kelvin really shines. The high-resolution measurement is able to capture these minute changes in resistance of the barrel. Many questions arise on how the Kelvin test works. The industry standard is a master comparison test. What we mean here is that a known electrically correct PCB is used to create the Kelvin master. This is done by performing several cycles (user-definable) on the PCB, and when complete, the master values are written.
The subsequent PCBs are then compared to the master values for evaluation. Differing from the forced barrel test, the theoretical values can be programmed in advance. However, due to the variances in plating from lot to lot, the minor differences in resistance can be fatal in repeatability even though fully conforming.
These options are available today to help capture electrical defects in plated barrels, whether they directly affect the electrical profile of the circuit board or are hiding in the functional spectrum of the barrel that does not affect board integrity. Consult with your ET department on how this may help you in the future. If you have questions, you can reach out to me as well.
The holidays are upon us. Be safe, keep your distance, and hug your family.
This column originally appeared in the November 2020 issue of Design007 Magazine.