Matched Length Does Not Always Equal Matched Delay


Reading time ( words)

In previous columns, I have discussed matched length routing and how matched length does not necessarily mean matched delay. But, all design rules, specified by chip manufacturers regarding high-speed routing, specify matched length--not matched delay. In this month’s column we’ll take a look at the actual differences between the two.

Typically, more than one layer change is required when routing traces to matched length. Figure 1 illustrates the DDR2 address bus routing I did in Altium Designer, my preferred layout tool. In this case, each address signal has four layer changes. The red and green traces are the top and bottom layers--which should be kept as short as possible--and the yellow and orange traces are inner layers embedded between the planes. This was a particularly difficult route as there were two DDR2 memory chips placed on both the top and bottom sides of the board, so each address signal had to go to four different chips and still maintain the correct delay.

 Olney_Delay.jpg

Figure 1: Matched delay T-section DDR2 address routing in Altium Designer.

The longest routes should be placed on the inner layers as this reduces electromagnetic radiation. With all other factors being equal, generally, a trace routed on the inner stripline layer exhibits 4-10 dB less noise than a trace routed on the outer microstrip  layer. Also, please note that there are more high harmonics on the top layer routing. The high-frequency components radiate more readily because their shorter wavelengths are comparable to trace lengths, which act as antennas. Consequently, although the amplitude of the harmonic frequency components decreases as the frequency increases, the radiated frequency varies depending on the trace’s characteristics.

Read the full column here.


Editor's Note: This column originally appeared in the March 2014 issue of The PCB Design Magazine.

Share




Suggested Items

HyperLynx: There’s an App for That

08/05/2022 | I-Connect007 Editorial Team
I recently spoke with Todd Westerhoff, product marketing manager for signal integrity software tools at Siemens. We discussed a new capability called HyperLynx Apps that offers a new take on traditional signal and power integrity analysis, and how that fits in with the Siemens plan to put SI and PI tools into the hands of more designers early in the design cycle.

Webinar Review: Thermal Integrity of High-Performance PCB Design

08/01/2022 | Andy Shaughnessy, Design007 Magazine
Electrical and mechanical engineers may be working on the same product development teams, but they speak different languages, and they have completely different objectives. As a result, these folks almost never use the same software tools. But Cadence’s new Celsius Thermal Solver is an exception to the rule. In a new CadenceTECHTALK webinar, “How Static and Dynamic IR Drop Analysis Can Help PCB Designs and Challenges,” product manager Melika Roshandell and SerDes SI/PI engineer Karthik Mahesh Rao explain how the EE and ME can both use the Celsius Thermal Solver to achieve their disparate objectives.

Rambus Driving a CXL Memory Option

06/30/2022 | Nolan Johnson, I-Connect007
In this interview with Arjun Bangre, director of product for high-speed interface IPs for PCI Express and CXL at Rambus, the discussion revolves around new developments in CXL, PCI Express, and interoperable IP solutions that Rambus has developed.



Copyright © 2022 I-Connect007. All rights reserved.