Reading time ( words)
Recently, I attended the Designers Council “Lunch and Learn” at Broadcom’s office in Orange County, California. One of the speakers at this event was Julie Ellis, a field applications engineer with TTM Technologies. She sat down with me to discuss her presentation and some of the ways fabricators can assist PCB designers.
Andy Shaughnessy: Julie, why don't you give us a little bit of background about yourself and your history in the industry?
Julie Ellis: I have a degree in electrical engineering and worked as a student and then as an engineer at Hughes Aircraft, which gave me great hands-on experience in RF/analog electronics and coaxial cable design, assembly, and test. After Hughes, I pursued technical sales as a manufacturer’s rep for semiconductors and circuit boards and represented Nan Ya PCB Corp. for ten years before rounding out my career in contract electronics manufacturing as a sales engineer and then global PCB commodity manager. I managed a fabricator’s ISO 9001 quality system and was a technical consultant and process and quality auditor for PCB, CM, and automotive customers before joining TTM.
Shaughnessy: I understand that you train inspectors?
Ellis: Yes. I'm a Certified IPC Trainer for acceptability of both circuit boards (IPC-A-600) and electronic assemblies (IPC-A-610). Untrained inspectors or clients cause tremendous schedule delays when they’re fearful of accepting a product that looks questionable to them, because they worry it could fail in the future. I really enjoy teaching students to understand the requirements and apply the standards to accept product with full confidence.
Shaughnessy: One thing the designers tell us in surveys is that they always want to know more about fab processes. They don’t get to visit board shops very often, if at all. If you can talk to the designers, what would say are a few things that they should do differently?
Ellis: Mainly, I would like to see them engage us, the field applications engineers, before they've started routing out their circuits. Multilayer PCB fabrication requires approximately 30 major process steps, including photoimaging and developing, etching, stripping, lamination, drilling, plating, and screening. Each process has physical or equipment limitations (tolerances) which can negatively impact the product yields or long-term reliability if the design is not optimized. We evaluate the attributes of the design to establish the guidelines for the designer, so their requirements don’t exceed process limitations when they go to fab. We will also create a preliminary stack-up to confirm their requirements for overall and Cu thickness, layer count, controlled impedance, drill and pad sizes can be met.
Secondly, I encourage them to visit one of our sites for a PCB 101 presentation and factory tour. We introduce the processes in a great visual presentation, so they understand what they’re seeing on the production floor.
Shaughnessy: If they get involved with the fabricator earlier, the earlier the better?
Ellis: Definitely! It's a lot easier to modify a design before – rather than after - they've done all the work routing.
Shaughnessy: Today, during your talk, you mentioned a really fascinating new technology that TTM has developed: The Next Generation SMV. Can you tell us a little bit about that?
Ellis: Sure. SMV® is the abbreviation for Stacked MicroVias, a technology which facilitates high density interconnects layer to layer by stacking laser microvias during sequential lamination cycles. SMV starts with a center lamination (sublam) that is drilled, plated, and etched and adds a new set of outer layers with each lamination cycle. A board with 3 layers of SMVs will travel around the production floor through lamination, drill, plate, and etch 3 times, which is very time-consuming.
NextGen-SMV™ also provides Z-axis connectivity from – and to – any layer, but in a single lamination cycle. Specially prepped single-sided cores are laser drilled and filled with copper conductive paste, stacked one on top of another from the bottom up and laminated in our Single Lamination Parallel Process, SLPP™. The pre-filled microvias don’t require plating or additional lamination cycles, so NextGen-SMV technology can be used when extremely fast turn time is required. And because very thin dielectrics are used, NextGen boards are sometimes thinner than standard ones.
Shaughnessy: So these technologies could be used under a micro BGA with lots of I/Os?
Ellis: Exactly. When we look at the grid array under a BGA, we have to consider how we are going to create conductive connections to every circuit board pad corresponding to the grid. The outer pads can be simply routed on the component layer, but when there’s not enough space to run traces between the pads, we have to use an additional layer for each inside row. As each row is connected, it opens routing for the next row.
Shaughnessy: It looks like it would be really hard to fabricate. I mean, if each row of the array pattern requires its own routing layer, it must be tough to build.
Ellis: It significantly increases complexity and requires enabling equipment and processing. Laser drills have to be used for microvias. And registration has to be dead-on, or the lasers can partially miss their landing pads and drill through the layers below. So we use Laser Direct Imaging, or LDI. And to plate these small holes, we developed reverse pulse plating processes with our plating chemistry supplier to assure continuous plating into single-ended (microvias that are drilled down and stop at the next layer) and high aspect ratio (drill depth:drill diameter) through-holes. It’s interesting to note that standard through-hole capability aspect ratio is 10:1, but because single-ended holes are so much more difficult to plate, microvia standard aspect ratio is preferred 0.5:1.