-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueOpportunities and Challenges
In this issue, our expert contributors discuss the many opportunities and challenges in the PCB design community, and what can be done to grow the numbers of PCB designers—and design instructors.
Embedded Design Techniques
Our expert contributors provide the knowledge this month that designers need to be aware of to make intelligent, educated decisions about embedded design. Many design and manufacturing hurdles can trip up designers who are new to this technology.
Manufacturing Know-how
For this issue, we asked our expert contributors to share their thoughts on the absolute “must-know” aspects of fab, assembly and test that all designers should understand. In the end, we’re all in this together.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - design007 Magazine
Beyond Design: Plane Crazy, Part 2
February 8, 2016 | Barry Olney, In-Circuit DesignEstimated reading time: 1 minute
In my recent four-part series on stackup planning, I described the best configurations for various stackup requirements. But I did not have the opportunity to delve into the use of planar capacitance to reduce AC impedance at frequencies above 1GHz, which is the region wherein bypass and decoupling capacitors dramatically lose their impact. In this column, I will flesh out this topic, and consider the effects of plane resonance on the power distribution network (PDN).
Figure 1 illustrates a 12-layer DDR3 board with six routing layers and six plane layers utilizing multiple technologies. This board must accommodate 40/80-ohm single-ended/differential impedance for DDR3, 90-ohm differential USB, and the standard 50/100-ohm digital impedances all on the same substrate. In order to reduce the layer count, it is important that these different technologies share the same layers. Plus, one needs to manage the return current paths and broadside coupling of the stripline configurations—quite a challenge!
The DDR3 matched delay signals are routed on the internal layers 3 & 4 and 9 & 10, which all use ground (GND) as the reference plane. To eliminate broadside coupling, the data lanes (eight in this case), differential strobes, and masks are routed on layers 3 & 4. And the adjacent traces are routed skewed or orthogonally. The address, control and command signals are routed together with the differential clock on layers 9 & 10. This separates the data lanes and address signals. Since DDR technology utilizes synchronous buses, the signals within the data lanes and within the address bus can be routed closely together, but the eight data lanes should be separated to avoid crosstalk.
As you can see, there are four planes in the center of the board, two power and two ground. This is where tight coupling, between adjacent planes, can be utilized to add planar capacitance at low cost and dramatically reduce the AC impedance at the high end. There are thin sheets of Isola 370HR 1080 prepreg (2.8 mils thick) between both planes pairs.
Given the effects of the capacitors equivalent series inductance (ESL) and mounting inductance, the added planar capacitance still reduces the overall impedance to approximately the target impedance up to 1GHz as in Figure 2. Now, this is not easy to do using standard stackups.
To read this entire article, which appeared in the January 2015 issue of The PCB Design Magazine, click here.
Suggested Items
Cogiscan Collaborates with Koh Young to Unveil how its Factory Insights Software Transforms Data into Action at IPC APEX Expo
03/28/2024 | Koh YoungKoh Young, the industry leader in True3D measurement-based inspection solutions, is excited to announce Factory Insights, the latest offering from Cogiscan, will be demonstrated alongside KSMART in Koh Young booth 2112 during IPC APEX Expo.
ASMPT to Exhibit Smart Manufacturing at IPC APEX EXPO 2024
03/27/2024 | ASMPTWith its innovative, data-driven Intelligent Factory concept and a comprehensive hardware and software portfolio around SMT production, market and innovation leader ASMPT will be a major presence at the IPC APEX EXPO 2024, the industry’s main event in California.
Semtech Pioneers the Path to 6G with Advanced 5G Wireless Technologies
03/27/2024 | BUSINESS WIRESemtech Corporation, a leader in high-performance semiconductors, IoT systems and cloud connectivity services, unveiled its latest innovations poised to shape the future of 5G and pave the way for 6G.
IDC: Half of Asia’s Top Firms to Embrace AI-Driven Headless BI and Analytics by 2026
03/27/2024 | IDCA recent IDC FutureScape report, IDC FutureScape: Worldwide Data and Analytics 2024 Predictions — Asia/Pacific (Excluding Japan) Implications, highlights that by 2026, 50% of Asia/Pacific-based Top 2000 organizations (A2000) will adopt AI-driven headless BI and analytics with chat, Q&A, and proactive notification functionality, quadrupling the number of users with access to contextual information.
AT&S Well Prepared to Benefit from AI Boom
03/26/2024 | AT&SThe rapid progress in the development of artificial intelligence promises to revolutionize all areas of daily life in the coming years. In order to operate such AI systems, an enormous amount of computing power is required, which is provided by a vast network of data centres.